Efficient hardware implementation of logarithmic units for reduced computational complexity in machine learning models
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Date
2026-02-08
Authors
Χαλίλ, Κοσμάς
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Abstract
This thesis explores methods for optimizing computational efficiency in machine learning systems, with a focus on reducing resource consumption during arithmetic operations. It is well established that multiplication and division operations are significantly more demanding in terms of computational time and hardware resources compared to addition and subtraction.
The aim of this work is to investigate the feasibility of transforming multiplication and division into logarithmic representations by leveraging logarithmic properties to express them as addition and subtraction. The core hypothesis is that this transformation can lead to a notable acceleration in processing without sacrificing the accuracy of machine learning model outputs.
A central contribution of this research is the hardware implementation of the proposed logarithmic units, using appropriate hardware description tools. The experimental evaluation compares the performance and resource usage of conventional arithmetic implementations with their logarithmic counterparts, highlighting potential benefits and trade-offs. The ultimate goal is to develop more efficient architectures suitable for deployment in resource-constrained environments such as embedded or edge computing systems.
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Keywords
Hardware accelerators, Machine learning