Data representation and hardware aspects in a fully-folded successive cancellation polar decoder
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Ανδριακόπουλος, Χρήστος
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Abstract
In this master thesis, is studied and implemented Error-Correction Codes system based
on Polar Codes. Polar Codes, introduced by Arıkan, are known for the capacity approach-
ing with low hardware complexity. We simulated a Polar Encoder/Decoder system on
Matlab in order to evaluate Polar Codes, and implemented in a FPGA device, afterwards.
At the beginning, is introduced the basic model of a digital communication system, ba-
sic units that consist of the entire communication system. After that, is introduced Polar
Codes, the construction procedure, and how can be implemented Polar Encoder and De-
coder in hardware. Chapter. 3 introduces decoding algorithms for Polar Codes, such as
Successive-Cancellation (SC), Successive-List-Cancellation (SLC) and Belief Propaga-
tion (BP). Also Chapter 3 discusses several state-of-the-art implementations of Polar De-
coders. In this master thesis, we focus on SC decoding algorithm due its simplicity which
facilitate the study of codes with relatively long block length. Due to limited resources
in a FPGA device, the technique of ‘folding’ applied, so the transformed DFG uses only
one processing unit (PB). A data representation scheme is introduced and it is shown to
lead to 30−50% reduction of required memory, for practical block lengths. In Chapter 5
shows implementation results and BER vs. noise level curves, while data are extracted
from Matlab simulations and FPGA implementation using the logic analyzer Chipscope.
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Keywords
Polar codes, Successive cancellation, FPGA