Algorithms and architectures for low-complexity high-order soft demappers
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Date
2024-10-15
Authors
Καλαμπούκας, Ανδρέας
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Abstract
In recent years, with the rapid advances in technology, there is an increased demand for fast data transmission and efficient utilization of the provided spectral area. In modern telecommunications systems, a basic process on the receiver side is the reliable detection and decoding of the received information symbols either sequentially or in parallel. To achieve this, decision making techniques are used, the successful decoding of a symbol is based on decisions for each symbol bit separately, based on probabilistic reasons. These techniques are applied to modern systems and are known as soft de-mapping methods for high order configurations, in order to achieve the desired spectral performance. Some modern communication standards suggest and include high-order configurations such as ITU-T G.hn (G.9960), DOCSIS 3.1 and DVB-C2 where they specify the 4096 order of QAM as the maximum choice. Therefore, the increase of modulation scheme plays a very important role in modern applications. However, increasing the order of modulation has the drawback that it increases the hardware complexity of the corresponding architecture, especially at the receiver side. To tackle this, numerous simplified de-mapping algorithms have been proposed in the recent research literature that target high order modulation schemes. The subject of this postgraduate diploma thesis is the review and presentation of the most ubiquitous algorithms and architectures for Soft De-mappers and the modeling, design and the hardware implementation of a novel algorithm and architecture, aiming at low complexity and easy integration into modern telecommunication applications.
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Keywords
High order modulation, Multiple binary search, Minimum comparisons, Soft demapper, PAM, LLR, FPGA