Simulation and HW implementation of calibration techniques for optical modules
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Date
2026-02-18
Authors
Μήλκας, Νικόλαος
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Abstract
Photonic Integrated Circuits (PICs) can pack many optical functions on a small chip, but in practice their performance changes with fabrication differences, temperature, and measurement noise. Because of this, a PIC can drift away from its optimal operating point (OOP) and needs a loop calibration that can automatically retune it while it is running. This thesis studies a digital calibration circuit that does exactly that, and it focuses on how to move from calibrating one tuning knob (one degree of freedom) to calibrating many tuning knobs (multiple degrees of freedom) in a structured and scalable way. In addition to simulation, this thesis develops a hardware-implementable digital circuit architecture for the calibration loop (block-level structure, scheduling, and update logic), intended to be portable to FPGA/ASIC flows. Full FPGA synthesis and on-board experimental validation are identified as the next step, but the core loop is presented in a form that is compatible with real-time hardware execution. The starting point is a standard approach based on adding a small periodic dither to a control input, measuring the response, and using synchronous detection to estimate whether the setting should move up or down to improve performance. In real hardware, however, this method can fail when the dither signal and the measured response are not aligned in time. That delay mismatch can come from ADC/DSP latency, buffering, filtering, routing delays, or timing jitter. When it happens, the demodulated signal can shrink in magnitude, change sign, or become noisy, which slows calibration down or can even destabilize the loop. To handle this, the thesis introduces an online delay-alignment step that continuously estimates the delay between the reference dither and the monitor signal using a robust cross-correlation method (after removing DC). By correcting this delay, the loop keeps a reliable direction signal and becomes more stable under practical timing uncertainty. Building on the stabilized single-DOF loop, a multi-DOF calibration architecture is developed that reuses the same signal-processing chain and updates the DOFs one at a time in time division (one coordinate updated per update instant), keeping separate state per DOF without redesigning the core algorithm. All ideas are tested with MATLAB simulations that model the circuit over time and show how each DOF changes during calibration. The results confirm stable convergence for a three-DOF setup and show that the same structure can be extended to higher-dimensional tuning (such as six DOFs) without changing the core design. The thesis also highlights the practical trade-offs between faster convergence and stability, and it closes with implementation notes aimed at an FPGA-friendly realization of delay alignment and scalable time-division multi-DOF tracking.
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Keywords
Optical circuits, Calibration