Implementation of the image compression standard JPEG using the RISC-V processor
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Date
2026-11-06
Authors
Καραμπάρπας, Δημοσθένης
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Abstract
This thesis explores the optimization and parallelization of the JPEG compression algorithm on the Snitch cluster, a highly specialized, heterogeneous RISC-V multi-core architecture. Designed for extreme energy efficiency and compute density, the Snitch architecture relies heavily on Tightly Coupled Data Memory (TCDM), Stream Semantic Registers (SSR), and asynchronous Data Movers (DM) rather than traditional hardware caches.
The research is divided into two primary phases: single-core micro-architectural optimization and cluster-level parallelization. Initially, the core JPEG pipeline was evaluated across Double Precision (FP64) and Packed SIMD (FP16) implementations. Despite the theoretical throughput advantages of half-precision vectorization, the FP64 implementation was selected as the optimal single-core baseline. By leveraging hardware-software co-design—such as zero-cost matrix transpositions via 4D SSR strides, Indirect SSRs (ISSR) for zig-zag routing, and hardware queues (copift)—the FP64 data path completely decoupled the Floating-Point Unit (FPU) from integer ALU bottlenecks, reducing execution time to 33,129 cycles per Minimum Coded Unit (MCU). A subsequent hybrid pipeline, which performs the compute stages in FP16 and widens the coefficients to FP64 with flh only for the zig-zag stage, reduced this further to 27,702 cycles per MCU (4.4x over the initial design) with a bit-identical output.
Subsequently, the pipeline was transitioned to the 8-core cluster utilizing a Tile-by-Tile Producer-Consumer model. Memory bandwidth and spatial contention were addressed by offloading all DMA transfers to the dedicated DM core and implementing Dual-Level Bank Staggering to eliminate TCDM lockstep bank collisions without wasting capacity on memory padding. Furthermore, instruction scheduling (software pipelining) was applied to the scalar Huffman encoder to mask RAW_LOAD_USE pipeline latencies.
Ultimately, the fully optimized multi-core implementation achieved a total compute time of 32,508 cycles to process 8 MCUs simultaneously. This yields a super-linear architectural speedup of 8.15x, proving that combining asynchronous memory orchestration with aggressive instruction-level prefetching allows the compute cores to reach peak mathematical throughput entirely unhindered by memory topology limits.
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Keywords
JPEG, Image compression, Snitch cluster, Stream Semantic Registers (SSR), Multi-core parallelization, Direct memory access (DMA), Memory bank conflicts, Packed SIMD FP16, Software pipelining, Energy-efficient computing