An application specific instruction set processor for cryptographic applications based on RISC-V architecture

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Θεοδωρόπουλος, Νικόλαος
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Nowadays, RISC-V instruction set architecture (ISA) is becoming increasingly popular in commercial CPU implementations. The benefits introduced by its open-source and simple design along with its ability to be customizable, make it a strong candidate, especially for inexpensive, low-power embedded devices. Implementations used in IoT applications can reap the benefits from an instruction set architecture like RISC-V, as energy efficiency is of paramount importance. Security and privacy of IoT networks have also been an ongoing debate and the most sought-after solutions are those achieving it with minimum performance requirements. There have been proposals that cryptographic hash functions and Blockchain technology could be parts of a potential solution to these problems. In this thesis, a RISC-V processor is presented and extended to make it suitable for cryptographic applications. Firstly, the RISC-V concept and architecture are introduced. Secondly, VexRiscv, the RISC-V core selected to host the cryptographic extensions, is studied. Subsequently, the cryptographic algorithm associated with this thesis and the technique used to accelerate its execution are thoroughly examined, with emphasis on details regarding the implementation. Finally, the design is implemented on a Field Programmable Gate Array, where its proper functioning is verified, initially via simulation and then through waveforms provided by an Integrated Logic Analyzer.
Processors, RISC-V, Instruction set architecture, VexRiscv, SHA-256, FPGA