Development and evaluation of fault-tolerance techniques for translation lookaside buffers (TLB)
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Date
2026-10-12
Authors
Αμπελικιώτης, Ορέστης
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Abstract
The scaling of integration technology, together with aggressive supply voltage reduction for power efficiency, has made the memory structures of modern processors increasingly prone to permanent faults caused by process variation, aging, and low-voltage operation.While these reliability problems have been studied extensively for cache memories, the Translation Lookaside Buffer (TLB), a small but performance-critical SRAM structure that caches virtual-to-physical address translations, has received comparatively little attention as a target for fault tolerance through graceful degradation.This thesis investigates the impact of permanent (hard) faults on the TLB and proposes a fault-tolerant TLB design based on the theory of Orthogonal Latin Squares (OLS). The technique systematically redistributes (permutes) the entries of a set-associative TLB so that faulty entries are spread as uniformly as possible across the sets, instead of clustering into a few sets that lose most or all of their ways. The permutation is computed offline from the fault map of the structure and is applied at run time with negligible overhead through a small set of permutation registers that are XOR-ed with the index. The approach adapts to the TLB the OLS-based inter-way permutation that Filippou et al. proposed for branch target buffers [1] and generalized to caches [2].The design is implemented and evaluated in the gem5 architectural simulator. The baseline x86 first-level data TLB (dTLB), which stock gem5 models as a flat, fully associative array, is extended with a set-associative organization and is subsequently augmented with the OLS permutation mechanism and a fault injection interface. At fault probabilities that correspond to published low-voltage operating points, the evaluation quantifies how much the faults degrade the performance of the dTLB without permutation and how much of the lost performance the proposed mechanism recovers.The evaluation comprises two full-system campaigns of 7,200 runs each on identical fault maps: a damage baseline without permutation, and the same runs with the permutation.The first establishes that the performance damage depends mainly on the distribution of the faults across the sets, in particular on the fully faulty sets at low associativity, and only in small part on the lost capacity. Associativity is therefore itself a fault-tolerance mechanism. The second measures what the permutation recovers. At two ways and the lower fault probability studied, it removes 86 % of the fully faulty sets and recovers 67 % of the IPC (instructions per cycle) loss caused by the faults. At the higher fault probability it removes about half of them and recovers 42 %. At four ways it removes every fully faulty set and recovers 41 % to 60 % of the loss, in part through its second objective, a more uniform distribution of the faulty entries across the sets. The permutation registers add only 0.1 % to 0.2 % to the storage of the array (about 1.4 % to 1.5 % together with the fault bit per entry that entry disabling needs in any case) and a single gate delay, which makes the scheme applicable to a first-level TLB.
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Keywords
Translation lookaside buffer, Fault tolerance, Orthogonal Latin squares