Design of high-speed clocked comparator with autozeroing techniques
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Date
2024-02
Authors
Κοντέλης, Σπυρίδων
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Abstract
This Master’s thesis deals with the design and development of a high-speed, high-sensitivity comparator, utilizing the autozeroing technique for improved input referred offset voltage. The overall comparator topology is based on a cascade connection of differential amplifiers and one dynamic latch comparator. It has been designed for use in high resolution, high sensitivity, and high sampling rate analog to digital converters, while additional techniques are applied for reducing the power and current consumption by about 30% compared to the conventional architectures, without affecting the targeting performance. The resulting circuit is evaluated at 50 Msps sampling rate and offers a minimum detectable differential input voltage of 435 μV, over process, voltage, and temperature corners, as well as over local mismatch variations which makes it suitable for 12-bit ADC. The circuit has been designed and verified using a TSMC 65nm CMOS technology.
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Keywords
Comparators, Autozeroing, Latch, Analog signal processing, Clocked comparators, High speed circuits