Exploring ternary logic for deep differentiable logic networks
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Date
2026-10-12
Authors
Ζαχιώτης, Δημήτριος
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Abstract
Efficient computation at inference time is a central concern in neural network research, and has led to techniques such as reduced numerical precision, binarized networks, and sparse architectures. A recent addition to this line of work is the logic gate network, a paradigm borrowed from digital circuit design in which each neuron is realized as a two-input binary logic gate rather than a weighted sum of inputs, enabling extremely efficient inference through direct hardware implementation. These networks have two limitations. Their accuracy is limited on harder benchmarks, and their behavior after logic synthesis, in terms of area, depth, and timing, has not been examined. This thesis extends differentiable logic gate networks from the binary to the ternary setting, motivated by the higher information capacity of a three-valued neuron, and builds the tooling needed to evaluate both network types at the hardware level.A balanced ternary encoding, {−1,0,1}, is adopted, and a curated set of 46ternary logic gates is presented, each derived from a small number of fundamental gates and their compositions, and defined in both a strict, discrete-valued form and a differentiable, real-valued relaxed form suitable for gradient-based training. Building on the original binary codebase accompanying prior work on differentiable logic gate networks, the implementation underlying this thesis extends the native CUDA training kernels, introduces a pure Python compilation pathway, and establishes a complete pipeline for translating trained ternary networks into synthesizable binary hardware.This pipeline encompasses a dual-rail encoding of ternary values into binary signal pairs, synthesis of the resulting binary gate designs on Cadence Genus, compilation of trained networks into efficient C-based executables, and generation of complete VHDL hardware descriptions. Network-level statistics, including area, depth, and timing, are computed both by aggregating pre-characterized gate-level values and, for a substantial subset of configurations, by synthesizing the complete trained circuit as a single unit, allowing the accuracy of the gate-level estimation approach to be validated against true whole-circuit synthesis.A design space exploration specific to the ternary setting is presented,empirically confirming that unbalanced and balanced ternary encodings are functionally interchangeable, while a fractional unbalanced encoding is not, due to its narrower representable range. A suitable subset of ternary gates is selected through a two-stage search, and the effect of Gaussian and Residual weight initialization on training stability and the resulting gate distributions is examined for both binary and ternary networks.Ternary and binary logic gate networks are then compared across the number of neurons, network depth, area, and latency, on both the MNIST and CIFAR-10 datasets. Ternary networks are found to require fewer total neurons than binary networks for comparable accuracy, consistent with their higher per-neuron information capacity; however, once ternary logic gates are expressed in binary form via the dual-rail encoding, this advantage does not extend to circuit depth, area, or latency, where binary networks generally achieve higher accuracy at equal cost. These findings suggest that, while ternary logic gate networks offer a genuine representational advantage in terms of neuron count, this advantage does not directly translate into an improvement in hardware efficiency once ternary values are expressed in binary form for comparison. Whether this reflects an inherent limitation of ternary logic gate networks, or is instead an artifact of the binary transformation used for comparison in this thesis, remains an open question for future work.
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Keywords
Neural networks, Logic gate networks, Ternary logic, Differentiable logic networks