Hardware implementation of error-spectrum-shaping digital filters
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Date
2026-10-12
Authors
Ευαγγελάτος, Γεώργιος
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Abstract
The focus of this thesis is the study of quantization noise in fixed-point digital Infinite Impulse Response (IIR) filters and the design of hardware architectures utilizing Error Spectrum Shaping (ESS) techniques. Initially, the basic principles of fixed-point arithmetic and wordlength rounding are introduced, highlighting their degrading impact on the Signal-to-Noise Ratio (SNR) and the Effective Number of Bits (ENOB) of digital signal processing systems.
The main architectural challenges of implementing optimal ESS methodologies in hardware are then examined. Particular emphasis is placed on the underlying error-shaping topologies, which require the extraction, scaling, and recursive feedback of the rounding error into the filter's datapath. The mathematical formulation of these optimal structures is analyzed, and the theoretical limits of quantization noise suppression are established through algorithmic simulations.
Transitioning from abstract theoretical models to physical realization, this thesis explores the hardware-software co-design and integration of the optimal ESS architectures. The digital filters are developed at the Register-Transfer Level (RTL) and implemented on a Zynq UltraScale+ System-on-Chip (SoC) Field-Programmable Gate Array (FPGA) utilizing an AXIbased communication interface. A Hardware-in-the-Loop (HIL) verification framework is established to confirm the exact bit-true equivalence of the physical hardware execution against the theoretical baseline models. Finally, the post-implementation results are presented, demonstrating the overall efficacy of the proposed hardware structures. The evaluation confirms that optimal ESS architectures significantly improve the output signal quality, pushing the effective SNR and resolution closer to floating-point boundaries. Ultimately, the results prove that these error-shaping techniques can be highly efficient in physical silicon, maintaining the computational, power, and area advantages of a fixed-point datapath while effectively overcoming its inherent quantization limitations.
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Keywords
Error spectrum shaping (ESS), Digital signal processing (DSP), Infinite impulse response (IIR), Power spectral density (PSD), Signal to noise ratio (SNR), Effective number of bits (ENOB), Register transfer level (RTL), Field programmable gate array (FPGA), VHSIC hardware description language (VHDL)