Hardware acceleration of AI/ML algorithm for fault detection in power distribution grid
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Date
2024-10-09
Authors
Κουκουλάς, Αλέξανδρος
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Abstract
This thesis deals with the hardware acceleration of a machine-learning model for fault detection in power distribution grids. The main purpose is to implement the fault location, identification, and type classification (FLITC) algorithm on hardware devices to increase the execution speed with little loss in accuracy. The algorithm involves Convolutional Neural Networks (CNNs) to identify faulty feeders and branches. It classifies the type of fault into eleven different categories and estimates its location. In particular, the FFNN model is responsible for detecting faulty feeders and is trained with a training dataset. A validation dataset is used to find the accuracy of its predictions. The trained model is initially quantized to reduce its size and processing latency. Three different quantization techniques are implemented: TensorFlow-Lite Dynamic Range, TensorFlow-Lite Full Integer, and Vitis-AI TensorFlow-2. After being quantized with the Vitis-AI TensorFlow-2 method, the model is compiled and executed on the FPGA hardware device Xilinx Zynq UltraScale+ MPSoC ZCU104 through a Deep learning Processor Unit (DPU). The FPGA execution is compared to the corresponding CPU and Raspberry Pi implementations of the TensorFlow-Lite models. Multithreading application using two DPUs was also tested, to reduce the latency further. In this way, more efficient fault detection in distribution networks is achieved, potentially leading to better network management.
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Keywords
Hardware acceleration, Artificial intelligence, Machine learning, Neural networks, Deep learning